Sciweavers

920 search results - page 89 / 184
» Computing the Frequency of Partial Orders
Sort
View
IEEEPACT
2007
IEEE
15 years 4 months ago
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
Brian Greskamp, Josep Torrellas
VTC
2006
IEEE
135views Communications» more  VTC 2006»
15 years 3 months ago
A Detection Algorithm for Clipped OFDM Signals Using the IDFT-Matrix
A major drawback of the Orthogonal Frequency Division Multiplex (OFDM) principle is the high dynamic range of the transmit signal. The transmit Power Amplifier (PA) and other ele...
Andreas Frotzscher, Peter Zillmann, Gerhard Fettwe...
VTC
2006
IEEE
15 years 3 months ago
Downlink DS-CDMA Transmission with Joint MMSE Equalization and ICI Cancellation
— The bit error rate (BER) performance of downlink DS-CDMA in a frequency-selective fading channel can be significantly improved by the use of frequency-domain equalization (FDE)...
Kazuaki Takeda, Koichi Ishihara, Fumiyuki Adachi
FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
15 years 3 months ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek
IEEEPACT
2003
IEEE
15 years 3 months ago
Picking Statistically Valid and Early Simulation Points
Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months to complete. ...
Erez Perelman, Greg Hamerly, Brad Calder