Sciweavers

4401 search results - page 610 / 881
» Computing with Default Logic
Sort
View
DAC
2005
ACM
16 years 6 months ago
Incremental retiming for FPGA physical synthesis
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
Deshanand P. Singh, Valavan Manohararajah, Stephen...
DAC
2006
ACM
16 years 6 months ago
Guiding simulation with increasingly refined abstract traces
Traces Kuntal Nanshi, Fabio Somenzi University of Colorado at Boulder ne abstraction refinement and simulation to provide a more efficient approach to checking invariant properti...
Kuntal Nanshi, Fabio Somenzi
DAC
2006
ACM
16 years 6 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
DAC
2006
ACM
16 years 6 months ago
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, ...
WWW
2009
ACM
16 years 5 months ago
Automated synthesis of composite services with correctness guarantee
In this paper, we propose a novel approach for composing existing web services to satisfy the correctness constraints to the design, including freeness of deadlock and unspecified...
Ting Deng, Jinpeng Huai, Xianxian Li, Zongxia Du, ...