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ISLPED
2003
ACM
111views Hardware» more  ISLPED 2003»
15 years 3 months ago
A low-power VLSI architecture for turbo decoding
Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block...
Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
JSAC
1998
110views more  JSAC 1998»
14 years 9 months ago
Turbo Decoding as an Instance of Pearl's "Belief Propagation" Algorithm
—In this paper, we will describe the close connection between the now celebrated iterative turbo decoding algorithm of Berrou et al. and an algorithm that has been well known in ...
Robert J. McEliece, David J. C. MacKay, Jung-Fu Ch...
ICC
2008
IEEE
15 years 4 months ago
Unveiling Near-Capacity Code Design: The Realization of Shannon's Communication Theory for MIMO Channels
— In this contribution we show how Shannon’s coding theory could be realized for Multiple-Input Multiple-Output (MIMO) channels with the aid of EXtrinsic Information Transfer (...
Soon Xin Ng, Jin Wang, Lajos Hanzo
GLOBECOM
2007
IEEE
15 years 4 months ago
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processin...
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon ...
TIT
2002
107views more  TIT 2002»
14 years 9 months ago
Constrained systems with unconstrained positions
We develop methods for analyzing and constructing combined modulation/error-correctiong codes (ECC codes), in particular codes that employ some form of reversed concatenation and w...
Jorge Campello de Souza, Brian H. Marcus, Richard ...