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» Concurrency, Time, and Constraints
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ICCD
2007
IEEE
322views Hardware» more  ICCD 2007»
15 years 8 months ago
Voltage drop reduction for on-chip power delivery considering leakage current variations
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 8 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ICCAD
2008
IEEE
133views Hardware» more  ICCAD 2008»
15 years 8 months ago
Module locking in biochemical synthesis
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...
Brian Fett, Marc D. Riedel
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
15 years 8 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
ICCAD
2006
IEEE
123views Hardware» more  ICCAD 2006»
15 years 8 months ago
A network-flow approach to timing-driven incremental placement for ASICs
We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits. FlowPlace includes: a) a t...
Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suth...