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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 8 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
15 years 8 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
CVPR
2010
IEEE
15 years 8 months ago
Recovering Fluid-type Motions Using Navier-Stokes Potential Flow
The classical optical flow assumes that a feature point maintains constant brightness across the frames. For fluidtype motions such as smoke or clouds, the constant brightness ass...
Feng Li, Liwei Xu, Philippe Guyenne, Jingyi Yu
WWW
2010
ACM
15 years 6 months ago
Selecting skyline services for QoS-based web service composition
Web service composition enables seamless and dynamic integration of business applications on the web. The performance of the composed application is determined by the performance ...
Mohammad Alrifai, Dimitrios Skoutas, Thomas Risse
CGO
2010
IEEE
15 years 6 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...