—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
We propose methods for segmenting a motion sequence into motion primitives, taking into account temporal constraints (continuity along the time axis). In the proposed methods, dyn...
In this paper, we develop heuristics for finding good starting points when solving large-scale nonlinear constrained optimization problems (COPs). We focus on nonlinear programmi...
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
In this paper, we propose a new scheduling method for asynchronous circuits in bundled-data implementation. The method is based on integer linear programming (ILP) which explores ...