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» Concurrent Error Detection Schemes for Involution Ciphers
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DSD
2006
IEEE
113views Hardware» more  DSD 2006»
13 years 8 months ago
Cascade Scheme for Concurrent Errors Detection
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 10 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey
TVLSI
2002
102views more  TVLSI 2002»
13 years 5 months ago
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time...
Ramesh Karri, Kaijie Wu
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 8 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
DFT
2007
IEEE
101views VLSI» more  DFT 2007»
14 years 18 days ago
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits
Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, vari...
Francesco Regazzoni, Thomas Eisenbarth, Johann Gro...