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» Concurrent Separation Logic for Pipelined Parallelization
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FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
13 years 11 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
CONCUR
2010
Springer
13 years 7 months ago
Reasoning about Optimistic Concurrency Using a Program Logic for History
Optimistic concurrency algorithms provide good performance for parallel programs but they are extremely hard to reason about. Program logics such as concurrent separation logic and...
Ming Fu, Yong Li, Xinyu Feng, Zhong Shao, Yu Zhang
IPPS
2000
IEEE
13 years 10 months ago
Register Assignment for Software Pipelining with Partitioned Register Banks
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...
Jason Hiser, Steve Carr, Philip H. Sweany, Steven ...
ESOP
2009
Springer
14 years 1 months ago
Deny-Guarantee Reasoning
Abstract. Rely-guarantee is a well-established approach to reasoning about concurrent programs that use parallel composition. However, parallel composition is not how concurrency i...
Mike Dodds, Xinyu Feng, Matthew J. Parkinson, Vikt...
CONCUR
2004
Springer
13 years 11 months ago
An Extensional Spatial Logic for Mobile Processes
Existing spatial logics for concurrency are intensional, in the sense that they induce an equivalence that coincides with structural congruence. In this work, we study a contextual...
Daniel Hirschkoff