51 search results - page 8 / 11 » Concurrent Table Accesses in Parallel Tabled Logic Programs |
IEEEPACT
2007
IEEE
15 years 3 months ago
2007
IEEE
In this paper we propose a unified architectural support that can be used flexibly for either soft-error protection or software bug detection. Our approach is based on dynamically...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
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DSD
2011
IEEE
13 years 9 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
ICFP
2008
ACM
15 years 9 months ago
2008
ACM
We describe an axiomatic extension to the Coq proof assistant, that supports writing, reasoning about, and extracting higher-order, dependently-typed programs with side-effects. C...
ISCA
1997
IEEE
15 years 1 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...