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122
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IANDC
2010
115views more  IANDC 2010»
15 years 24 days ago
18th International Conference on Concurrency Theory
We consider message sequence charts enriched with timing constraints between pairs of events. As in the untimed setting, an infinite family of time-constrained message sequence cha...
Luís Caires, Vasco Thudichum Vasconcelos
ENTCS
2007
116views more  ENTCS 2007»
15 years 3 months ago
Handling Model Changes: Regression Testing and Test-Suite Update with Model-Checkers
Several model-checker based methods to automated test-case generation have been proposed recently. The performance and applicability largely depends on the complexity of the model...
Gordon Fraser, Bernhard K. Aichernig, Franz Wotawa
144
Voted
ACSD
2009
IEEE
149views Hardware» more  ACSD 2009»
15 years 10 months ago
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations
We propose a general method to characterize and synthesize correctness-preserving, asynchronous wrappers for synchronous processes on a globally asynchronous locally synchronous (...
Dumitru Potop-Butucaru, Robert de Simone, Yves Sor...
IPPS
2002
IEEE
15 years 8 months ago
Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit speci...
John O'Donnell
118
Voted
ICCAD
1999
IEEE
99views Hardware» more  ICCAD 1999»
15 years 7 months ago
Concurrent logic restructuring and placement for timing closure
: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and the...
Jinan Lou, Wei Chen, Massoud Pedram