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ISVC
2007
Springer
15 years 10 months ago
ChipViz : Visualizing Memory Chip Test Data
This paper presents a technique that allows test engineers to visually analyze and explore within memory chip test data. We represent the test results from a generation of chips al...
Amit P. Sawant, Ravi Raina, Christopher G. Healey
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
15 years 9 months ago
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform ...
Irith Pomeranz, Sudhakar M. Reddy
HICSS
2003
IEEE
179views Biometrics» more  HICSS 2003»
15 years 9 months ago
JUMBL: A Tool for Model-Based Statistical Testing
Statistical testing of software based on a usage model is a cost-effective and efficient means to make inferences about software quality. In order to apply this method, a usage m...
Stacy J. Prowell
VTS
1997
IEEE
96views Hardware» more  VTS 1997»
15 years 8 months ago
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
ACSAC
2003
IEEE
15 years 9 months ago
Synthesizing Test Data for Fraud Detection Systems
This paper reports an experiment aimed at generating synthetic test data for fraud detection in an IP based videoon-demand service. The data generation verifies a methodology pre...
Emilie Lundin Barse, Håkan Kvarnström, ...