4299 search results - page 293 / 860 » Concurrent Test Generation |
125
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DATE
2008
IEEE
15 years 11 months ago
2008
IEEE
This paper presents a time-domain jitter expansion technique for high-speed digital bit sequence jitter testing. While jitter expansion has been applied to phase noise measurement...
125
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ICST
2008
IEEE
15 years 11 months ago
2008
IEEE
Testing remains a major challenge for model transformation development. Test models that are used as test data for model transformations, are constrained by various sources of kno...
127
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DATE
2007
IEEE
15 years 11 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
141
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ETS
2006
IEEE
15 years 10 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
115
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...