4299 search results - page 301 / 860 » Concurrent Test Generation |
143
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ICSEA
2009
IEEE
15 years 11 months ago
2009
IEEE
—In this paper, it is shown that synthetic images can be used to test specific use cases of a lane tracking algorithm which has been developed by Audi AG. This was achieved by s...
126
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ASM
2005
ASM
15 years 10 months ago
2005
ASM
Abstract. This paper presents a new approach to model and test hierarchical Graphical User Interfaces (GUIs). We exploit the structure of Hierarchical Finite State Machines (HFSMs)...
144
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ASPDAC
2004
ACM
15 years 10 months ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
148
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VTS
2002
IEEE
15 years 9 months ago
2002
IEEE
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
142
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DATE
2000
IEEE
15 years 9 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...