4299 search results - page 371 / 860 » Concurrent Test Generation |
111
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ATS
2009
IEEE
15 years 11 months ago
2009
IEEE
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
136
Voted
DSD
2005
IEEE
15 years 10 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
140
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ITC
2000
IEEE
15 years 9 months ago
2000
IEEE
In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson ...
134
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ITC
1999
IEEE
15 years 9 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
120
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EURODAC
1994
IEEE
15 years 9 months ago
1994
IEEE
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...