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VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
16 years 5 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
SAC
2004
ACM
15 years 10 months ago
WebUml: reverse engineering of web applications
Web applications have become complex and crucial for many firms, especially when combined with areas such as CRM (Customer Relationship Management) and BPR (Business Process Reen...
Carlo Bellettini, Alessandro Marchetto, Andrea Tre...
118
Voted
DATE
2007
IEEE
172views Hardware» more  DATE 2007»
15 years 11 months ago
Diagnosis, modeling and tolerance of scan chain hold-time violations
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
Ozgur Sinanoglu, Philip Schremmer
ISSTA
2006
ACM
15 years 11 months ago
DSD-Crasher: a hybrid analysis tool for bug finding
DSD-Crasher is a bug finding tool that follows a three-step approach to program analysis: D. Capture the program’s intended execution behavior with dynamic invariant detection....
Christoph Csallner, Yannis Smaragdakis
SIGMOD
2000
ACM
141views Database» more  SIGMOD 2000»
15 years 9 months ago
Counting, Enumerating, and Sampling of Execution Plans in a Cost-Based Query Optimizer
Testing an SQL database system by running large sets of deterministic or stochastic SQL statements is common practice in commercial database development. However, code defects oft...
Florian Waas, César A. Galindo-Legaria