Sciweavers

4299 search results - page 403 / 860
» Concurrent Test Generation
Sort
View
VTS
2000
IEEE
126views Hardware» more  VTS 2000»
15 years 10 months ago
Static Compaction Techniques to Control Scan Vector Power Dissipation
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
ECOOP
1997
Springer
15 years 10 months ago
Near Optimal Hierarchical Encoding of Types
A type inclusion test is a procedure to decide whether two types are related by a given subtyping relationship. An efficient implementation of the type inclusion test plays an impo...
Andreas Krall, Jan Vitek, R. Nigel Horspool
SRDS
1993
IEEE
15 years 10 months ago
Bayesian Analysis for Fault Location in Homogeneous Distributed Systems
We propose a simple and practical probabilistic comparison-based model, employing multiple incomplete test concepts, for handling fault location in distributed systems using a Bay...
Yu Lo Cyrus Chang, Leslie C. Lander, Horng-Shing L...
ITC
1994
IEEE
151views Hardware» more  ITC 1994»
15 years 10 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
Nur A. Touba, Edward J. McCluskey
APLAS
2008
ACM
15 years 8 months ago
The Complexity of Coverage
Abstract. We study the problem of generating a test sequence that achieves maximal coverage for a reactive system under test. We formulate the problem as a repeated game between th...
Krishnendu Chatterjee, Luca de Alfaro, Rupak Majum...