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ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
16 years 1 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
GECCO
2004
Springer
114views Optimization» more  GECCO 2004»
15 years 10 months ago
A Study of the Role of Single Node Mutation in Genetic Programming
In this paper we examine the effects of single node mutations on trees evolved via genetic programming. The results show that neutral mutations are less likely for nodes nearer th...
Wei Quan, Terence Soule
163
Voted
BMCBI
2005
98views more  BMCBI 2005»
15 years 4 months ago
Iterative approach to model identification of biological networks
Background: Recent advances in molecular biology techniques provide an opportunity for developing detailed mathematical models of biological processes. An iterative scheme is intr...
Kapil G. Gadkar, Rudiyanto Gunawan, Francis J. Doy...
IISWC
2008
IEEE
15 years 11 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
CCGRID
2006
IEEE
15 years 11 months ago
Proposal of MPI Operation Level Checkpoint/Rollback and One Implementation
With the increasing number of processors in modern HPC(High Performance Computing) systems, there are two emergent problems to solve. One is scalability, the other is fault tolera...
Yuan Tang, Graham E. Fagg, Jack Dongarra