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ITC
1993
IEEE
148views Hardware» more  ITC 1993»
15 years 7 months ago
DELTEST: Deterministic Test Generation for Gate-Delay Faults
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
Udo Mahlstedt
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
16 years 3 months ago
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaud...
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
15 years 26 days ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
IWANN
2009
Springer
15 years 9 months ago
Aiding Test Case Generation in Temporally Constrained State Based Systems Using Genetic Algorithms
Generating test data for formal state based specifications is computationally expensive. This paper improves a framework that addresses this issue by representing the test data ge...
Karnig Derderian, Mercedes G. Merayo, Robert M. Hi...
ICST
2009
IEEE
15 years 25 days ago
An Evaluation of Model Checkers for Specification Based Test Case Generation
Under certain constraints the test case generation problem can be represented as a model checking problem, thus enabling the use of powerful model checking tools to perform the te...
Gordon Fraser, Angelo Gargantini