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VTS
1998
IEEE
88views Hardware» more  VTS 1998»
15 years 7 months ago
Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
Bruce F. Cockburn, Albert L.-C. Kwong
ICST
2010
IEEE
15 years 1 months ago
Timed Moore Automata: Test Data Generation and Model Checking
Abstract—In this paper we introduce Timed Moore Automata, a specification formalism which is used in industrial train control applications for specifying the real-time behavior ...
Helge Löding, Jan Peleska
114
Voted
ISSRE
2007
IEEE
15 years 4 months ago
Generating Trace-Sets for Model-based Testing
Model-checkers are powerful tools that can find individual traces through models to satisfy desired properties. These traces provide solutions to a number of problems. Instead of...
Birgitta Lindström, Paul Pettersson, Jeff Off...
ET
1998
99views more  ET 1998»
15 years 3 months ago
A Behavior Model for Next Generation Test Systems
Defining information required by automatic test systems frequently involves a description of system behavior. To facilitate capturing the required behavior information in the cont...
Lee A. Shombert, John W. Sheppard
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
16 years 3 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...