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DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 9 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
CORR
2004
Springer
100views Education» more  CORR 2004»
15 years 3 months ago
Test Collections for Patent-to-Patent Retrieval and Patent Map Generation in NTCIR-4 Workshop
This paper describes the Patent Retrieval Task in the Fourth NTCIR Workshop, and the test collections produced in this task. We perform the invalidity search task, in which each p...
Atsushi Fujii, Makoto Iwayama, Noriko Kando
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
15 years 7 months ago
RESIST: a recursive test pattern generation algorithm for path delay faults
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
Karl Fuchs, Michael Pabst, Torsten Rössel
EDCC
2005
Springer
15 years 8 months ago
PathCrawler: Automatic Generation of Path Tests by Combining Static and Dynamic Analysis
Abstract. We present the PathCrawler prototype tool for the automatic generation of test-cases satisfying the rigorous all-paths criterion, with a user-defined limit on the number...
Nicky Williams, Bruno Marre, Patricia Mouy, Muriel...
111
Voted
OSDI
2008
ACM
16 years 3 months ago
KLEE: Unassisted and Automatic Generation of High-Coverage Tests for Complex Systems Programs
We present a new symbolic execution tool, KLEE, capable of automatically generating tests that achieve high coverage on a diverse set of complex and environmentally-intensive prog...
Cristian Cadar, Daniel Dunbar, Dawson R. Engler