309 search results - page 8 / 62 » Concurrent timing optimization of latch-based digital system... |
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
121
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TVLSI
2010
14 years 4 months ago
2010
With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fail...
SOFSEM
2007
Springer
15 years 3 months ago
2007
Springer
Digital technology is increasingly deployed in safety-critical situations. This calls for systematic design and verification methodologies that can cope with three major sources o...
ICCSA
2004
Springer
15 years 3 months ago
2004
Springer
The paper presents an improved scheme for the visualization of 3D terrain in real-time using Digital Elevation Model (DEM). The method is primarily based on a modified version of R...
83
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PATMOS
2005
Springer
15 years 3 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...