3616 search results - page 104 / 724 » Conditional Memory Ordering |
ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
- This paper presents program pulse characterization in an 8-Mb BJT-selected Phase-Change Memory test chip. Experimental results of the impact of the bit-line resistance over progr...
111
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CRYPTO
2003
Springer
15 years 10 months ago
2003
Springer
In 1992, Dwork and Naor proposed that e-mail messages be accompanied by easy-to-check proofs of computational effort in order to discourage junk e-mail, now known as spam. They pro...
171
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RTCSA
2008
IEEE
15 years 11 months ago
2008
IEEE
Nowadays, systems often integrate a variety of applications whose service requirements are heterogeneous. Consequently, systems must be able to concurrently serve applications whi...
108
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ISCA
2006
IEEE
15 years 10 months ago
2006
IEEE
We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread c...
156
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FTTCS
2006
15 years 4 months ago
2006
Data sets in large applications are often too massive to fit completely inside the computer's internal memory. The resulting input/output communication (or I/O) between fast ...