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ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Fast, predictable and low energy memory references through architecture-aware compilation
The design of future high-performance embedded systems is hampered by two problems: First, the required hardware needs more energy than is available from batteries. Second, curren...
Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefa...
ASPDAC
2004
ACM
118views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Minimization of memory size for heterogeneous MDDs
Abstract— In this paper, we propose exact and heuristic algorithms for minimizing the memory size for heterogeneous Multivalued Decision Diagrams (MDDs). In a heterogeneous MDD, ...
Shinobu Nagayama, Tsutomu Sasao
ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
15 years 9 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya
AH
2006
Springer
15 years 8 months ago
Recomindation: New Functions for Augmented Memories
Advances in technological support for augmented personal memories make possible new ways of enhancing the process of product recommendation. Instead of simply analyzing information...
Carolin Plate, Nathalie Basselin, Alexander Kr&oum...
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
15 years 8 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...