3616 search results - page 141 / 724 » Conditional Memory Ordering |
146
Voted
ISMVL
2000
IEEE
15 years 9 months ago
2000
IEEE
A sequential realization of multiple-output logic functions is presented. A conventional sequential realization is based on SBDDs (Shared reduced ordered Binary Decision Diagrams)...
141
Voted
ESOP
1999
Springer
15 years 9 months ago
1999
Springer
Abstract. A race condition is a situation where two threads manipulate a data structure simultaneously, without synchronization. Race conditions are common errors in multithreaded ...
138
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LCTRTS
2010
Springer
15 years 12 months ago
2010
Springer
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
156
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CF
2009
ACM
15 years 11 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
164
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ESA
2004
Springer
15 years 10 months ago
2004
Springer
Sample sort, a generalization of quicksort that partitions the input into many pieces, is known as the best practical comparison based sorting algorithm for distributed memory para...