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VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
16 years 5 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
172
Voted
VEE
2009
ACM
240views Virtualization» more  VEE 2009»
15 years 11 months ago
Memory buddies: exploiting page sharing for smart colocation in virtualized data centers
Many data center virtualization solutions, such as VMware ESX, employ content-based page sharing to consolidate the resources of multiple servers. Page sharing identifies virtual...
Timothy Wood, Gabriel Tarasuk-Levin, Prashant J. S...
146
Voted
ISCA
1996
IEEE
126views Hardware» more  ISCA 1996»
15 years 9 months ago
Memory Bandwidth Limitations of Future Microprocessors
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory laten...
Doug Burger, James R. Goodman, Alain Kägi
ISPASS
2010
IEEE
15 years 7 months ago
Understanding transactional memory performance
Abstract—Transactional memory promises to generalize transactional programming to mainstream languages and data structures. The purported benefit of transactions is that they ar...
Donald E. Porter, Emmett Witchel
HPCA
2005
IEEE
16 years 5 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob