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IEEEPACT
2002
IEEE
15 years 11 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
15 years 10 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
176
Voted
CASES
2004
ACM
15 years 10 months ago
Reducing energy consumption of queries in memory-resident database systems
The tremendous growth of system memories has increased the capacities and capabilities of memory-resident embedded databases, yet current embedded databases need to be tuned in or...
Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T...
153
Voted
ISCAS
2008
IEEE
122views Hardware» more  ISCAS 2008»
16 years 20 days ago
A nano-CMOS process variation induced read failure tolerant SRAM cell
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
ISPAN
2005
IEEE
15 years 12 months ago
A Fast Noniterative Scheduler for Input-Queued Switches with Unbuffered Crossbars
Most high-end switches use an input-queued or a combined input- and output-queued architecture. The switch fabrics of these architectures commonly use an iterative scheduling syst...
Kevin F. Chen, Edwin Hsing-Mean Sha, S. Q. Zheng