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DATE
2004
IEEE
147views Hardware» more  DATE 2004»
15 years 10 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
DCC
2008
IEEE
15 years 8 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
GRAPHICSINTERFACE
2007
15 years 7 months ago
Optimized subdivisions for preprocessed visibility
This paper describes a new tool for preprocessed visibility. It puts together view space and object space partitioning in order to control the render cost and memory cost of the v...
Oliver Mattausch, Jirí Bittner, Peter Wonka...
AAAI
2004
15 years 7 months ago
Compressing Pattern Databases
A pattern database is a heuristic function stored as a lookup table which stores the lengths of optimal solutions for instances of subproblems. All previous pattern databases had ...
Ariel Felner, Ram Meshulam, Robert C. Holte, Richa...
206
Voted
PSTV
1992
113views Hardware» more  PSTV 1992»
15 years 7 months ago
Coverage Preserving Reduction Strategies for Reachability Analysis
We study the effect of three new reduction strategies for conventional reachability analysis, as used in automated protocol validation algorithms. The first two strategies are imp...
Gerard J. Holzmann, Patrice Godefroid, Didier Piro...