3616 search results - page 290 / 724 » Conditional Memory Ordering |
136
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WMTE
2002
IEEE
15 years 9 months ago
2002
IEEE
Our research aims at defining models and software tools in order to provide learners with a training memory. This memory is a computer-based space where a learner can organize and...
147
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IPPS
2000
IEEE
15 years 9 months ago
2000
IEEE
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
133
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INFOCOM
1999
IEEE
15 years 9 months ago
1999
IEEE
One of the key design issues for the new generation IP routers is the route lookup mechanism. For each incoming IP packet, the IP routing requires to perform a longest prefix match...
122
Voted
ISCA
1999
IEEE
15 years 9 months ago
1999
IEEE
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
129
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VLSID
1999
IEEE
15 years 9 months ago
1999
IEEE
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...