3616 search results - page 71 / 724 » Conditional Memory Ordering |
151
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BIRTHDAY
2012
Springer
14 years 5 days ago
2012
Springer
We propose a new countermeasure to protect block ciphers implemented in leaking devices, at the intersection between One-Time Programs and Boolean masking schemes. First, we show t...
148
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ARCS
2010
Springer
15 years 11 months ago
2010
Springer
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
137
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ASPDAC
2007
ACM
15 years 8 months ago
2007
ACM
Due to the extremely large sizes of power grids, IR drop analysis has become a computationally challenging problem both in terms of runtime and memory usage. It has been shown in [...
150
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CCGRID
2001
IEEE
15 years 8 months ago
2001
IEEE
High performance computing on parallel architectures currently uses different approaches depending on the hardory model of the architecture, the abstraction level of the programmi...
115
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ICASSP
2011
IEEE
14 years 8 months ago
2011
IEEE
Due to computational bounds, most SVM-based phonotactic language recognition systems consider only low-order n-grams (up to n = 3), thus limiting the potential performance of this...