Sciweavers

3616 search results - page 72 / 724
» Conditional Memory Ordering
Sort
View
HPCA
2007
IEEE
16 years 4 months ago
A Burst Scheduling Access Reordering Mechanism
Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a r...
Jun Shao, Brian T. Davis
HIPC
2000
Springer
15 years 8 months ago
Memory Consistency and Process Coordination for SPARC Multiprocessors
Abstract. Simple and unified non-operational specifications of the three memory consistency models Total Store Ordering (TSO), Partial Store Ordering (PSO), and Relaxed Memory Orde...
Lisa Higham, Jalal Kawash
DAM
2007
100views more  DAM 2007»
15 years 4 months ago
Memory management optimization problems for integrated circuit simulators
In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to ...
Timothée Bossart, Alix Munier Kordon, Franc...
DAC
1995
ACM
15 years 8 months ago
Delayed Frontal Solution for Finite-Element Based Resistance Extraction
To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution ...
N. P. van der Meijs, Arjan J. van Genderen
MANSCI
2010
95views more  MANSCI 2010»
15 years 2 months ago
Using Scheduled Ordering to Improve the Performance of Distribution Supply Chains
We study a supply chain with one supplier and many retailers that face exogenous endcustomer demands. The supplier and the retailers all try to minimize their own inventory-relate...
Lucy Gongtao Chen, Srinagesh Gavirneni