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ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 10 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
142
Voted
SPAA
2003
ACM
15 years 9 months ago
Performance comparison of MPI and three openMP programming styles on shared memory multiprocessors
When using a shared memory multiprocessor, the programmer faces the selection of the portable programming model which will deliver the best performance. Even if he restricts his c...
Géraud Krawezik
ASPLOS
2012
ACM
14 years 8 days ago
Applying transactional memory to concurrency bugs
Multithreaded programs often suffer from synchronization bugs such as atomicity violations and deadlocks. These bugs arise from complicated locking strategies and ad hoc synchroni...
Haris Volos, Andres Jaan Tack, Michael M. Swift, S...
FPGA
2001
ACM
139views FPGA» more  FPGA 2001»
15 years 9 months ago
A memory coherence technique for online transient error recovery of FPGA configurations
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
Wei-Je Huang, Edward J. McCluskey
137
Voted
CODES
2000
IEEE
15 years 9 months ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf