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FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
13 years 10 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
BMCBI
2010
156views more  BMCBI 2010»
13 years 6 months ago
PeakAnalyzer: Genome-wide annotation of chromatin binding and modification loci
Background: Functional genomic studies involving high-throughput sequencing and tiling array applications, such as ChIP-seq and ChIP-chip, generate large numbers of experimentally...
Mali Salmon-Divon, Heidi Dvinge, Kairi Tammoja, Pa...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
13 years 12 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
POPL
2007
ACM
14 years 6 months ago
Modular type classes
ML modules and Haskell type classes have proven to be highly effective tools for program structuring. Modules emphasize explicit configuration of program components and the use of...
Derek Dreyer, Robert Harper, Manuel M. T. Chakrava...
FCCM
2004
IEEE
152views VLSI» more  FCCM 2004»
13 years 10 months ago
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki...