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» Configurable Transactional Memory
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ASPLOS
2010
ACM
15 years 3 months ago
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the memory subsystem. If resource sharing is unfair, some applications can be delayed significantl...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
15 years 3 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
DATE
2004
IEEE
127views Hardware» more  DATE 2004»
15 years 3 months ago
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
M. Bellato, Paolo Bernardi, D. Bortolato, A. Cande...
IPPS
2010
IEEE
14 years 9 months ago
Clustering JVMs with software transactional memory support
Affordable transparent clustering solutions to scale non-HPC applications on commodity clusters (such as Terracotta) are emerging for Java Virtual Machines (JVMs). Working in this ...
Christos Kotselidis, Mikel Luján, Mohammad ...