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TVLSI
2008
117views more  TVLSI 2008»
14 years 11 months ago
Configurable VLSI Architecture for Deblocking Filter in H.264/AVC
In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result s...
Chung-Ming Chen, Chung-Ho Chen
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
15 years 5 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
DAC
1999
ACM
16 years 24 days ago
Memory Exploration for Low Power, Embedded Systems
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
Wen-Tsong Shiue, Chaitali Chakrabarti
FPL
2000
Springer
115views Hardware» more  FPL 2000»
15 years 3 months ago
Efficient Self-Reconfigurable Implementations Using On-chip Memory
abstract the dynamic nature of a computation to embedded data memory (which is accessible on-chip). The dynamic nature of a computation corresponds to the dynamic features of its i...
Sameer Wadhwa, Andreas Dandalis
ASPLOS
2004
ACM
15 years 5 months ago
Programming with transactional coherence and consistency (TCC)
Transactional Coherence and Consistency (TCC) offers a way to simplify parallel programming by executing all code within transactions. In TCC systems, transactions serve as the fu...
Lance Hammond, Brian D. Carlstrom, Vicky Wong, Ben...