734 search results - page 99 / 147 » Configurable Transactional Memory |
116
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DFT
2009
IEEE
15 years 8 months ago
2009
IEEE
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
106
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IPPS
2002
IEEE
15 years 7 months ago
2002
IEEE
Eclipse is a heterogeneous multiprocessor architecture for high-performance media processing, including highdefinition MPEG encoding/decoding. The scalable architecture framework ...
IFL
2000
Springer
15 years 5 months ago
2000
Springer
Sac is a functional array processing language particularly designed with numerical applications in mind. In this field the runtime performance of programs critically depends on the...
104
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CAL
2002
15 years 1 months ago
2002
Embedded systems commonly execute one program for their lifetime. Designing embedded system architectures with configurable components, such that those components can be tuned to t...
101
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IISWC
2008
IEEE
15 years 8 months ago
2008
IEEE
Commercial server applications remain memory bound on modern multiprocessor systems because of their large data footprints, frequent sharing, complex non-strided access patterns, ...