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135
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ASPLOS
1989
ACM
15 years 7 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
166
Voted
CASES
2007
ACM
15 years 7 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
145
Voted
CF
2007
ACM
15 years 7 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
152
Voted
ICASSP
2009
IEEE
15 years 7 months ago
Optimized opportunistic multicast scheduling (OMS) over heterogeneous cellular networks
Optimized opportunistic multicast scheduling (OMS) has been studied previously by the authors for homogeneous cellular networks, where the problem of efficiently transmitting a co...
Tze-Ping Low, Man-On Pun, Yao-Win Peter Hong, C.-C...
139
Voted
BROADNETS
2004
IEEE
15 years 7 months ago
Random Asynchronous Wakeup Protocol for Sensor Networks
This paper presents Random Asynchronous Wakeup (RAW), a power saving technique for sensor networks that reduces energy consumption without significantly affecting the latency or c...
Vamsi Paruchuri, Shivakumar Basavaraju, Arjan Durr...
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