A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Optimized opportunistic multicast scheduling (OMS) has been studied previously by the authors for homogeneous cellular networks, where the problem of efficiently transmitting a co...
Tze-Ping Low, Man-On Pun, Yao-Win Peter Hong, C.-C...
This paper presents Random Asynchronous Wakeup (RAW), a power saving technique for sensor networks that reduces energy consumption without significantly affecting the latency or c...