136 search results - page 14 / 28 » Congestion reduction in traditional and new routing architec... |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
MICRO
1994
IEEE
15 years 1 months ago
1994
IEEE
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
ARC
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. The novel design of high-speed and low-energy FPGA routing architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. For that purpose,...
FPGA
2008
ACM
14 years 11 months ago
2008
ACM
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
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GECCO
2004
Springer
15 years 2 months ago
2004
Springer
Abstract. Designing storage area networks is an NP-hard problem. Previous work has focused on traditional algorithmic techniques to automatically determine fabric requirements, net...