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ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
15 years 9 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
DATE
2003
IEEE
137views Hardware» more  DATE 2003»
15 years 9 months ago
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branche...
Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexa...
ASPLOS
1992
ACM
15 years 8 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
COOTS
2001
15 years 5 months ago
Multi-Dispatch in the Java Virtual Machine: Design and Implementation
Mainstream object-oriented languages, such as C++ and Java1 , provide only a restricted form of polymorphic methods, namely uni-receiver dispatch. In common programming situations...
Christopher Dutchyn, Paul Lu, Duane Szafron, Steve...
VTS
2011
IEEE
278views Hardware» more  VTS 2011»
14 years 7 months ago
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories
This paper proposes an adaptive multi-bit error correcting code for phase change memories that provides a manifold increase in the lifetime of phase change memories thereby making...
Rudrajit Datta, Nur A. Touba