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HPCA
2003
IEEE
16 years 5 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
FDL
2004
IEEE
15 years 8 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
NETWORKS
2011
14 years 11 months ago
On cut-based inequalities for capacitated network design polyhedra
In this article we study capacitated network design problems. We unify and extend polyhedral results for directed, bidirected and undirected link capacity models. Based on valid i...
Christian Raack, Arie M. C. A. Koster, Sebastian O...
ASPDAC
2012
ACM
279views Hardware» more  ASPDAC 2012»
14 years 14 days ago
Block-level 3D IC design with through-silicon-via planning
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
SECON
2008
IEEE
15 years 11 months ago
Gateway Design for Data Gathering Sensor Networks
—Innovation in gateways for data gathering sensor networks has lagged compared to advances in mote-class devices, leaving us with a limited set of options for deploying such syst...
Raluca Musaloiu-Elefteri, Razvan Musaloiu-Elefteri...