In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigu...
Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-M...
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
In mobile ad hoc networks, synchronous communication mechanisms appear to be not suitable, since these assume that the involved entities are present at the same time during the in...
Abstract. Digital signal processing and control (DSPC) tools allow application developers to assemble systems by connecting predefined components in signal–flow graphs and by h...
Abstract—Overlay network design for topic-based publish/subscribe systems is of primary importance because the overlay directly impacts the system’s performance. Determining a ...