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ISCAS
2006
IEEE
101views Hardware» more  ISCAS 2006»
15 years 10 months ago
A cost-effective reconfigurable accelerator for platform-based SOC design
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigu...
Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-M...
WMPI
2004
ACM
15 years 10 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
MIDDLEWARE
2004
Springer
15 years 10 months ago
Designing a context-aware middleware for asynchronous communication in mobile ad hoc environments
In mobile ad hoc networks, synchronous communication mechanisms appear to be not suitable, since these assume that the involved entities are present at the same time during the in...
Mirco Musolesi
134
Voted
CONCUR
2003
Springer
15 years 10 months ago
A Compositional Semantic Theory for Synchronous Component-based Design
Abstract. Digital signal processing and control (DSPC) tools allow application developers to assemble systems by connecting predefined components in signal–flow graphs and by h...
Barry Norton, Gerald Lüttgen, Michael Mendler
ICDCS
2010
IEEE
15 years 8 months ago
Divide and Conquer Algorithms for Publish/Subscribe Overlay Design
Abstract—Overlay network design for topic-based publish/subscribe systems is of primary importance because the overlay directly impacts the system’s performance. Determining a ...
Chen Chen, Hans-Arno Jacobsen, Roman Vitenberg