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VLSISP
2008
147views more  VLSISP 2008»
15 years 3 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
DAC
2002
ACM
16 years 6 months ago
Compiler-directed scratch pad memory hierarchy design and management
One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly impo...
Mahmut T. Kandemir, Alok N. Choudhary
ICFP
2006
ACM
16 years 4 months ago
Design patterns as higher-order datatype-generic programs
Design patterns are reusable abstractions in object-oriented software. However, using current mainstream programming languages, these elements can only be expressed extra-linguist...
Jeremy Gibbons
ICCD
2006
IEEE
312views Hardware» more  ICCD 2006»
16 years 1 months ago
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
Kimiyoshi Usami, Naoaki Ohkubo
RTSS
2007
IEEE
15 years 11 months ago
A UML-Based Design Framework for Time-Triggered Applications
Time-triggered architectures (TTAs) are strong candidate platforms for safety-critical real-time applications. A typical time-triggered architecture is constituted by one or more ...
Kathy Dang Nguyen, P. S. Thiagarajan, Weng-Fai Won...