In this paper, we have presented the design and evaluation of a compiler system, called APE,for automatic parallelization of scientific and engineering applications on distributed...
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core speci...
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...