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2004
IEEE
152views Hardware» more  DATE 2004»
15 years 7 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
CCS
2006
ACM
15 years 7 months ago
A scalable approach to attack graph generation
Attack graphs are important tools for analyzing security vulnerabilities in enterprise networks. Previous work on attack graphs has not provided an account of the scalability of t...
Xinming Ou, Wayne F. Boyer, Miles A. McQueen
DSN
2004
IEEE
15 years 7 months ago
The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices
Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS de...
A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rang...
CF
2006
ACM
15 years 7 months ago
An efficient cache design for scalable glueless shared-memory multiprocessors
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
Alberto Ros, Manuel E. Acacio, José M. Garc...
COLT
2006
Springer
15 years 7 months ago
Logarithmic Regret Algorithms for Online Convex Optimization
In an online convex optimization problem a decision-maker makes a sequence of decisions, i.e., chooses a sequence of points in Euclidean space, from a fixed feasible set. After ea...
Elad Hazan, Adam Kalai, Satyen Kale, Amit Agarwal
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