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» Considerations for the design of exergames
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ANCS
2007
ACM
15 years 1 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
ASPDAC
2007
ACM
77views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Hippocrates: First-Do-No-Harm Detailed Placement
Physical synthesis optimizations and engineering change orders typically change the locations of cells, resize cells or add more cells to the design after global placement. Unfort...
Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-J...
SP
2010
IEEE
210views Security Privacy» more  SP 2010»
15 years 1 months ago
Reconciling Belief and Vulnerability in Information Flow
Abstract—Belief and vulnerability have been proposed recently to quantify information flow in security systems. Both concepts stand as alternatives to the traditional approaches...
Sardaouna Hamadou, Vladimiro Sassone, Catuscia Pal...
GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 1 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja