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ASPDAC
2007
ACM
86views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Fast Buffered Delay Estimation Considering Process Variations
- Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations...
Tien-Ting Fang, Ting-Chi Wang
TVLSI
2008
176views more  TVLSI 2008»
14 years 9 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
85
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FDL
2003
IEEE
15 years 2 months ago
Design and Power Analysis in SysteC of an I2C Bus Driver
The paper presents a methodology to integrate information on power consumption in a high level functional description of a System-on-chip. The power dissipated during the executio...
Marco Caldari, Massimo Conti, Paolo Crippa, Simone...
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
15 years 6 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
DAC
2005
ACM
15 years 10 months ago
Full-chip analysis of leakage power under process variations, including spatial correlations
In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correla...
Hongliang Chang, Sachin S. Sapatnekar