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» Constant Multipliers for FPGAs
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ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
15 years 10 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
15 years 5 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...
119
Voted
TC
2002
15 years 1 months ago
Finite Field Multiplier Using Redundant Representation
This article presents simple and highly regular architectures for finite field multipliers using a redundant representation. The basic idea is to embed a finite field into a cyclo...
Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, Shuhon...
141
Voted
FPGA
2008
ACM
151views FPGA» more  FPGA 2008»
15 years 3 months ago
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
Michael T. Frederick, Arun K. Somani
FPL
2005
Springer
98views Hardware» more  FPL 2005»
15 years 7 months ago
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
Peter Jamieson, Jonathan Rose