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ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 1 months ago
A timing analysis algorithm for circuits with level-sensitive latches
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
Jin-fuw Lee, Donald T. Tang, C. K. Wong
ICDE
2009
IEEE
130views Database» more  ICDE 2009»
15 years 11 months ago
Recursive Computation of Regions and Connectivity in Networks
In recent years, the data management community has begun to consider situations in which data access is closely tied to network routing and distributed acquisition: examples includ...
Mengmeng Liu, Nicholas E. Taylor, Wenchao Zhou, Za...
SIAMCOMP
2000
125views more  SIAMCOMP 2000»
14 years 9 months ago
Approximating the Stretch Factor of Euclidean Graphs
There are several results available in the literature dealing with efficient construction of t-spanners for a given set S of n points in Rd. t-spanners are Euclidean graphs in whic...
Giri Narasimhan, Michiel H. M. Smid
JVCA
2010
94views more  JVCA 2010»
14 years 8 months ago
A hybrid approach for simulating human motion in constrained environments
We present a new algorithm to generate plausible motions for high-DOF human-like articulated figures in constrained environments with multiple obstacles. Our approach is general ...
Jia Pan, Liangjun Zhang, Ming C. Lin, Dinesh Manoc...
ALGORITHMICA
2011
14 years 4 months ago
All-Pairs Bottleneck Paths in Vertex Weighted Graphs
Let G = (V, E, w) be a directed graph, where w : V → R is an arbitrary weight function defined on its vertices. The bottleneck weight, or the capacity, of a path is the smalles...
Asaf Shapira, Raphael Yuster, Uri Zwick