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143
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VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
15 years 7 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
15 years 7 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
15 years 7 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
144
Voted
ICRA
1998
IEEE
142views Robotics» more  ICRA 1998»
15 years 7 months ago
Lagrangian Relaxation Neural Networks for Job Shop Scheduling
Abstract--Manufacturing scheduling is an important but difficult task. In order to effectively solve such combinatorial optimization problems, this paper presents a novel Lagrangia...
Peter B. Luh, Xing Zhao, Yajun Wang
137
Voted
IEEEPACT
1998
IEEE
15 years 7 months ago
A Matrix-Based Approach to the Global Locality Optimization Problem
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
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