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DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 10 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
CONCUR
2006
Springer
15 years 10 months ago
Controller Synthesis for MTL Specifications
Abstract. We consider the control problem for timed automata against specifications given as MTL formulas. The logic MTL is a linear-time timed temporal logic which extends LTL wit...
Patricia Bouyer, Laura Bozzelli, Fabrice Chevalier
166
Voted
KR
2000
Springer
15 years 10 months ago
Reduction rules and universal variables for first order tableaux and DPLL
Recent experimental results have shown that the strength of resolution, the propositional DPLL procedure, the KSAT procedure for description logics, or related tableau-like implem...
Fabio Massacci
AAAI
1990
15 years 7 months ago
Exploiting Locality in a TMS
This paper presents a new approach for exploiting Truth Maintenance Systems(TMSs) which makes them simpler to use without necessarily incurring a substantial performance penalty. ...
Johan de Kleer
DIAGRAMS
2010
Springer
15 years 7 months ago
An Attention Based Theory to Explore Affordances of Textual and Diagrammatic Proofs
Shimojima and Katagiri have demonstrated that diagrams reduce "inferential load" during reasoning by scaffolding visual-spatial aspects of memory. In response, we wondere...
Peter Coppin, Jim Burton, Stephen Hockema