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CONCUR
2004
Springer
15 years 10 months ago
Model Checking Timed Automata with One or Two Clocks
In this paper, we study model checking of timed automata (TAs), and more precisely we aim at finding efficient model checking for subclasses of TAs. For this, we consider model ch...
François Laroussinie, Nicolas Markey, Ph. S...
FPL
2001
Springer
107views Hardware» more  FPL 2001»
15 years 9 months ago
Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays
In this paper we present a new method of integrating the placement and routing stages in the physical design of channel-based architectures, and present the first implementation o...
John Karro, James P. Cohoon
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 8 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
IAT
2009
IEEE
15 years 8 months ago
Developing a Deterministic Patrolling Strategy for Security Agents
Abstract—Developing autonomous systems that patrol environments for detecting intruders is a topic of increasing relevance in security applications. An important aspect of these ...
Nicola Basilico, Nicola Gatti, Francesco Amigoni
COLING
2010
14 years 12 months ago
FactRank: Random Walks on a Web of Facts
Fact collections are mostly built using semi-supervised relation extraction techniques and wisdom of the crowds methods, rendering them inherently noisy. In this paper, we propose...
Alpa Jain, Patrick Pantel